1. Field of Invention
The present invention relates to a method of fabricating a polysilicon layer. More particularly, the present invention relates to a method of fabricating a polysilicon layer through lateral crystallization using partially melted amorphous silicon inside a trench as nucleation seeds.
2. Description of Related Art
Low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD) differs from a conventional amorphous silicon thin film transistor liquid crystal display (α-Si TFT-LCD) in that an electron mobility as high as 200 cm2/V-sec can be reached. Hence, each thin film transistor device may occupy a smaller area so that a higher opening rate and hence a brighter display with smaller power consumption can be obtained. In addition, an increase in electron mobility also opens up the possibility of fabricating a portion of the driver circuit and the thin film transistor together on a glass substrate. Ultimately, reliability of the liquid crystal display panel is improved and cost of producing each display is reduced. Therefore, LTPS TFT-LCD has a fabrication cost considerably lower than α-Si TFT-LCD. Other advantages of the LTPS TFT-LCD has includes a slim package, a light body and a relatively high resolution. This renders the LTPS TFT-LCD especially suitable for implementing on portable and energy-short mobile terminal products.
The channel layer of the thin film transistor inside a LTPS TFT-LCD is formed in an excimer laser annealing (ELA) process. In general, quality of the channel layer depends largely on the average size of the polysilicon grains and their uniformity. However, the average size of the polysilicon grains and their uniformity are directly related to the energy provided to the excimer laser in the annealing process.
FIGS. 1A to 1C are schematic cross-sectional views showing the steps for producing a conventional polysilicon layer. As shown in FIG. 1A, a substrate 100 such as a glass substrate is provided. A buffer layer 102 is formed over the substrate 100. In general, the buffer layer 102 is a composite layer that includes a silicon nitride layer or a silicon oxide layer.
As shown in FIGS. 1B and 1C, an amorphous silicon layer 104 is formed over the buffer layer 102. Thereafter, an excimer laser annealing (ELA) process is conducted. The amount of radiation energy on the amorphous silicon layer 104 provided by the excimer laser is so carefully controlled that the entire amorphous silicon layer 104 almost completely melts. Hence, only a few seed of crystallization remains on top of the buffer layer 102. Thereafter, the melted silicon will start to crystallize from the seeds of crystallization to form a polysilicon layer 106 that contains lots of non-uniformly distributed grain boundaries.
In the aforementioned excimer laser annealing process, if the energy provided to the excimer laser exceeds the super lateral growth (SLG) point, density distribution of the seed of crystallization may drop to a very low value within a transient interval. The sudden loss of seed of crystallization may lead to the production of lots of small and highly non-uniform grains. Thus, energy to the excimer laser must be precisely controlled in order to fabricate a polysilicon layer with large and uniform grains therein. In other words, the process window is very small.
FIG. 2 is a perspective view showing a buffer layer with lots of openings capable of facilitating the fabrication of a polysilicon layer over the buffer layer. As shown in FIG. 2, a substrate 200 such as a glass substrate is provided. A buffer layer 202 is formed over the substrate 200. In general, the buffer layer 202 is a composite layer that includes a silicon nitride layer and a silicon oxide layer. To increase the grain size and uniformity of the polysilicon layer and widen the process window of the fabrication process, a plurality of openings arranged into an array are formed on the buffer layer 202. These openings 204 play a significant role during the excimer laser annealing process. During the annealing process, the amorphous silicon (not shown) outside the openings 204 melts completely and the silicon turns into a liquid state. However, some amorphous silicon (not shown) at the bottom of the openings 204 may remain solid and act as initiation sites for the lateral growth of crystal to form a polysilicon layer. In other words, crystallization starts out from the openings 204. Consequently, the quantity and distribution of the seed of crystallization is precisely controlled.
FIG. 3 is a top view showing the grain boundaries of a polysilicon layer formed with an array of openings on the buffer layer as shown in FIG. 2. Since the amorphous silicon at the bottom of the openings 204 does not melt completely, crystallization of liquid silicon grows laterally from the bottom of each opening 204. Due to the lateral growth of crystal from the bottom of the openings 204, a grain boundary 300 is formed between neighboring openings 204. In general, locations of the grain boundaries are directly related to the distance of separation between the openings. Because the openings 204 have an array arrangement, grain growth in the x and the y direction is influenced by the separation of neighboring openings. Thus, although the formation of an array of openings in the buffer layer is able to control grain size and uniformity, size of grains is still subjected to an intrinsic restriction.